Fabricating 3D ICs using die stacking technology can minimize the impact of altering existing manufacturing technology and equipment. Testing and design-for-testability forms an integral part of 3D IC manufacturing. In traditional IC manufacturing, wafers are probed and individual dies tested (wafer sorting) before they are packaged. In 3D integration, there are a number of challenges that must be overcome before bonding wafers. For example, test access is limited: at any given point during wafer fabrication only the top side of the TSVs can be probed while the bottoms are buried in the substrate. In addition, measurements are single-ended: limited test access results in single-ended measurements, for example, direct current (DC) probing results in current flow only through the surface of a TSV. Further, new types of defects arise, e.g., random open defects can result from dislocations, oxygen trapped on the surface, void formation, and/or mechanical failures. Accordingly, the yield of 3D ICs can be considerably increased if pretested dies can be bonded on top of each other.
A known approach for testing TSVs includes using a TSV test circuit 101 to charge/discharge and sense the voltage level at a TSV top end, as depicted in FIG. 1. The TSV acts as a load capacitor with respect to a test stimulus 103. A Flip Flop (FF) 105 is used to store the OutSensing signal at the TSV Test Circuit output compared to the signal from the Delay Circuit 107. The FF 105 then delivers the TSV Test Result 109. The approach is capable of detecting breaks, voids, and pin-hole type of process-related defects in TSVs with a high defect sensitivity, e.g., approximately 2 femtofarad (fF). However, one test circuit is required for each TSV, which is impractical for testing high density TSVs in wide input/output (I/O) area for memory-on-logic stacking applications. Further, this methodology cannot be implemented to test TSV daisy chains and, therefore, must rely on package level tests, which result in low yields.
A need therefore exists for methodology enabling testing of TSVs at the wafer-level (pre-bond) and also at the package-level (post bond) while maintaining high defect sensitivity.